1. Field of the Invention
Example embodiments of the present invention relate to methods of forming patterns and/or capacitors for semiconductor devices using the same. For example, at least one example embodiments of the present invention is directed to a method of forming semiconductor structures including a pattern having an increased and/or higher aspect ratio, and methods of forming a capacitor for a semiconductor device using the same.
2. Description of the Related Art
Related art dynamic random access memory (DRAM) devices may have a unit cell including an access transistor and a storage capacitor. Increased integration of semiconductor devices may require a smaller storage capacitor. Recent methods for manufacturing semiconductor devices have formed capacitors with larger storing capacitance and/or reduced size.
Capacitance C of a capacitor is expressed as the following equation (1).
                    C        =                              ɛ            0                    ⁢          ɛ          ⁢                      A            d                                              (        1        )            
In the above equation (1), ∈0 represents a dielectric constant of a vacuum and ∈ represents a dielectric constant of a dielectric layer of a capacitor. ‘A’ represents an effective surface area of a lower electrode and ‘d’ represents a thickness of the dielectric layer.
As shown in equation (1), storage capacitance of a capacitor may be directly proportional to an effective surface area of a lower electrode and a dielectric constant of a dielectric layer and may be inversely proportional to a thickness of a dielectric layer. Thus, according to the equation (1), an increase in the effective surface area of a lower electrode may be used for increasing the storage capacitance. For example, a lower electrode of a capacitor may be formed into a cylindrical shape having a larger height than width such that a surface area of the lower electrode is increased.
FIG. 1 is a cross sectional view illustrating a lower electrode of a related art capacitor for a semiconductor device. As shown, a plurality of cylindrical lower electrodes 16 may be formed on a semiconductor substrate 10. Each of the cylindrical lower electrodes 16 may have a larger height than width and may be arranged on the substrate close to each other. A cylindrical lower electrode 16 having a larger height than width may have a higher aspect ratio. An insulation interlayer 12 may be formed on the substrate 10 and a contact pad 14 may be formed into the insulation interlayer 12. The cylindrical lower electrode 16 may contact the contact pad 14.
A mold layer (not shown) having an opening may be used to form the cylindrical lower electrode 16. The mold layer having an opening may be formed on the substrate 10, and a thin layer may be formed (e.g., continuously formed) on a surface of the mold layer, sidewalls and bottom of the opening. The thin layer may be separated by a cell unit through a node separation process, and the mold layer may be completely removed from the substrate 10. The node-separated thin layer may be formed into a cylindrical lower electrode for a capacitor on the substrate 10.
A dry etching process may not sufficiently remove the mold layer from the substrate 10 because the mold layer may comprise oxide. In addition, a residual mold layer may remain on the substrate 10 even after the etching process. Accordingly, the mold layer may be removed from the substrate 10 by a wet etching process using an etchant containing water such as Limulus Amoebocyte Lysate (LAL) solution that is a mixture of ammonium fluoride (NH4F), hydrogen fluoride (HF) and water (H2O).
However, foreign matters 18 in FIG. 2 may accumulate between the cylindrical lower electrodes 16 when the mold layer is removed by a wet etching process. In particular, as shown in FIG. 2, when the foreign matters 18 accumulate between the cylindrical lower electrodes 16, the lower electrodes 16 may break and/or lean against each other and cause processing failures such as a two-bit failure. A two-bit failure is when two neighboring lower electrodes 16 make contact with each other. Foreign matters 18 may result from water in the etchant.
When a wet etching process for removing the mold layer from the substrate 10 is completed, water of the etchant may remain in the processing residuals distributed on a surface of the substrate 10. When the substrate experiencing the wet etching process is moved for a subsequent process, the water in the residuals may chemically react with air and oxidize resulting in the formation of the foreign matters between the cylindrical lower electrodes 16 on the substrate 10.
A cleansing process for removing the foreign matters 18 from the substrate 10 just before a dielectric layer is formed on the lower electrode 16 may be needed. An aqueous hydrogen fluoride (HF) solution may be used as a cleaning solution of the cleaning process. However, the foreign matters may still be found between the lower electrodes 16 despite the cleaning process because the water in the aqueous hydrogen fluoride (HF) solution may also create the foreign matters between the lower electrodes 16.